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Dr P Ramanathan
B. E (Electronics and Instrumnetation.), M. E. (VLSI Design), Ph D (VLSI Design)
Engineering
ramanathan.p@manipaldubai.com
Experience
Dr.P.Ramanathan had his Bachelors in Electronics and Instrumentation Engineering in 1997 from Bharathiar University Coimbatore.  He has more than 10 years of teaching experience and 5 years of research experience. He started his career as a Lecturer in Electronics and Communication Engineering Department at A.V.C College of Engineering, Mayiladuthurai in the year 1999.  In the year 2000, Dr.P.Ramanathan joined Electronics and Communication Engineering Department of PSG College of Technology, Coimbatore. He completed his Master Degree in VLSI Design during May 2006 under Anna University, Chennai.  In the year 2005 he became senior lecturer in the Department of Electronics and Communication Engineering, PSG College of Technology, Coimbatore.  In the year 2006, he joined Ph. D programme in PSG College of Technology and completed in May 2010.  Dr.P.Ramanathan  published  15 research papers in Journals, International and National Conference. He has organized several short term training programmes in the area of VLSI Design at PSG College of Technology. He was the Joint Secretary of the PSG Tech Alumni Association for the period 2008-2010. He was also a tutor for a B.E and M.E batch of Students’ at PSG College of Technology. He was an Examiner at Anna University, Chennai and Anna University, Coimbatore.  Currently Dr.P.Ramanathan  is working as an Assistant Professor in Electronics and Communication  Engineering Department, Manipal University Dubai Campus.
Areas of Interest in teaching
His areas of interest include VLSI Design and Biomedical Engineering. At Manipal University Dubai Campus, he is teaching Analog Electronics and Problem Solving using Computer.
Top 5 research publications/ Projects
Top 5 research publications/ Projects
 
  • P.Ramanathan and Dr.P.T.Vanathi (2009), ‘Power Delay optimized adder for Multiply and Accumulate Units’, International Journal of Digital Signal Processing, Vol. 9, Issue 1, pp.11-17.
  • P.Ramanathan and Dr.P.T.Vanathi (2009), ‘High Speed Multiplier Design using Decomposition Logic’, Serbian Journal of Electrical Engineering, Vol.6, No.1, pp.33-42.
  • P.Ramanathan and Dr.P.T.Vanathi (2009), ‘A Novel Power Delay Optimized 32-bit Parallel Prefix Adder for High Speed Computing’, International Journal of Recent Trends in Engineering,
  • P.Ramanathan and Dr.P.T.Vanathi (2009), ‘Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product’, International Journal of Electronics, Circuits and Systems, Vol.3, No.1, pp.66-70.
  • P.Ramanathan, Dr.P.T.Vanathi, T.S.Keirthana and N. Sindhu Maheswari (2010), ‘Comparative Analysis of Power Delay Product Between Different Families with Achievement of Reduction using Decomposition Algorithm’, International Journal of Power, Control, Signal and Computation, Vol.1, No.1, pp.41-46.